I am extremely happy that this year, me, and a few colleagues back from the DIAS lab of EPFL, published a new book pertaining to designing databases that can fully exploit and utilize modern hardware! My co-authors include Prof. Anastasia Ailamaki, my PhD advisor and director of the DIAS lab, Dr. Erietta Liarou, doing her post-doc at the lab, and Dr. Pinar Tözün and Dr. Danica Porobic, who are PhD graduates of the lab. The book is titled “Databases on Modern Hardware: How to Stop Underutilization and Love Multicores”, and published by Morgan & Claypool. You can find it by clicking the link below:
Book "Databases on Modern Hardware: How to Stop Underutilization and Love Multicores", published by Morgan & Claypool in August 2017
The book is the culmination of a long process of gathering knowledge from our own and related work. We gradually built up our knowledge through our research work and the creation and presentation of multiple tutorials at conference venues such as SIGMOD 2014 (citation) and ICDE 2015 (citation). This book is a great resource for database researchers and designers who are interested in making databases efficient on modern hardware and would like to get the lay of the land by reading related work.
The book begins by explaining and visualizing the hardware trends that have shaped modern hardware. Recent hardware provide abundant parallelism such as multi-core processors with advanced micro-architectural features. Traditionally designed data management systems do not fully exploit modern hardware as they face inherent scalability problems. The book focuses on design techniques for databases to fully exploit and utilize modern hardware and avoid a huge waste of hardware resources and energy.
The book’s material is divided in two dimensions of scalability: vertical and horizontal. The vertical dimension revolves around instruction- and data-level parallelism opportunities in a core, and techniques that ameliorate the utilization of a processor’s microarchitectural features by improving cache locality at the right level of the memory hierarchy. The horizontal dimension focuses on scalability bottlenecks at the level of multi-socket multi-core architectures, including ways of systematically eliminating such bottlenecks in online transaction processing workloads, how to exploit data and work sharing opportunities for analytical workloads, and advanced scheduling mechanisms that are aware of the non-uniformity of memory accesses and bandwidth.